| 摘要 |
PURPOSE:To facilitate the working of bit lines, improve the yield, reduce para sitic capacitance and parasitic resistance, and increase operation speed, by making two adjacent memory cells in the word line direction share a bit line pair. CONSTITUTION:In the storage device, a shared structure by two adjacent memory cells C11, C12 in the word line direction is realized. The two memory cells C11, C12 share a bit line pair BL1, BLB1, and two word lines are shared by the memory cells C11, C12. Each of the word lines is connected with each of the memory cells C11, C12. Two adjacent memory cells in the word line direction and cells which are adjacent to the two memory cells in the bit line direction are connected together by using a diffusion layer or a wiring layer, and sharing by four adjacent memory cells is realized. Thereby the working of the bit lines BL1, BLB2 is facilitated, the yield is improved, and the reliability to stress migration and electric migration can be improved. |
