发明名称 SYNCHRONOUS CIRCUIT
摘要 PURPOSE: To synchronize plural transmission/reception devices and to integrate plural CODEC on a single integrated circuit by separating reception/transmission pulses with frame synchronizing separation pulses. CONSTITUTION: The frame synchronizing separation pulses FSEP are supplied from a line 314 to a synchronizing unit 306 and received synchronizing pulses FSR0-FSR3 delayed by the connection time of FSEP are generated for corresponding transmission synchronizing pulses by using a system clock signal inputted form a line 321. The received synchronizing pulses FSR0-FSR3 are transmitted to respective CODEC 302-305 at prescribed delayed time from corresponding transmitted synchronizing pulses FST0-FST3. Thus, three integrated circuit terminals are saved and four CODEC can be stored in a standard package by generating four received pulses from FSEP.
申请公布号 JPH07221746(A) 申请公布日期 1995.08.18
申请号 JP19950013269 申请日期 1995.01.04
申请人 AMERICAN TELEPH & TELEGR CO <ATT> 发明人 BENJIYAMIN HEIYAZU EBAATO;ROBAATO HENRII BUEIDEN;EDOWAADO JIYOSEFU JIMENII JIYUNIA
分类号 H03L7/00;H04J3/06;H04L7/08 主分类号 H03L7/00
代理机构 代理人
主权项
地址