Vektorprozessoren und Vektorregistersteuerung.

摘要

A multiprocessor sharing a vector register (VR) with several scalar units (SU0, SU1). To each address in each bank (B0 to B7) of the vector register belong a plurality of memory modules (10), each for storing a vector element. The number of memory modules belonging to an address being equal to the number of scalar units sharing the vector register. Each of the memory modules is identified by a new address number which is created by combining the address number and a SU number. SU numbers are numbers identifying the scalar units. Vector data relevant to each scalar unit is stored in memory modules having the same SU number as the scalar unit concerned. The data is stored with interleaving in all of the banks. When a scalar unit accesses vector data, it sends out a first address number and the vector length of the requested vector data. An address generator automatically generates new address numbers in succession, combining the address number and the SU number, and the data is accessed. When some of the scalar units are not used, the memory modules relevant to the unused scalar units can be utilised for increasing the memory capacity of the active scalar units.