| 摘要 |
PURPOSE:To ensure an economical multiplication and division without lowering the operational speed even in case the arithmetic data length may be increased, by obtaining the value of normalization of the multiplier and others through reference of the logarithmic table and then using the value as the decimal part of the logarithm. CONSTITUTION:Logarithm call-out circuit (a) of multiplier/divider consists of shift register AR3 which is capable of the parallel input and output, logarithmic table read-out exclusive memory ROM3, counter CN1, buffer register BR3, inverter INV, AND circuit and others. While cologarithm call-out circuit (b) comprises address register AR4, cologarithmic table ROM4, shift controller CON1 to calculate the shift amount, shift register BR4 which is capable of the parallel input and output and others. Positive binary number A(000101) is set to AR3, and at the same time the initial value (101) is loaded to CN1. As a result, clock pulse e is supplied, and A is sifted to the left with 3-bit left shift, thus obtaining (1010000). In such way, the normalization is completed for binary number A. |
