EXCEPTION HANDLING CIRCUIT AND METHOD

摘要

A microprocessor circuit (106) monitors addresses generated by the microprocessor (100) to check for various address-exception conditions. Fetch-exception status bits are generated for each instruction byte to indicate whether an address-exception was detected for each respective byte address. Once fetches are performed, the fetch-exception status bits are fed to an instruction buffer (118) with the corresponding instruction bytes, where they are maintained until execution. Decode logic (140) of an instruction control unit (112) analyzes the fetch-exception status bits upon execution, and generates an exception before the corresponding exception-causing instruction (200) is executed. Address-exceptions occurring as the result of operand accesses are handled immediately. The operand access causing the exception is aborted, and the decode of the following instruction (210) is modified to generate a micro-interrupt. A micro-interrupt routine determines the cause of the interrupt, and generates the appropriate exception. For breakpoint exceptions on operand accesses, the micro-interrupt routine re-executes the breakpoint-causing instruction (332) to completion before generating the appropriate exception.