| 摘要 |
Burst refresh mode circuitry is provided for a memory (100) having cells (112) in rows and columns, sense amplifiers (110) and Latch N/Latch P driver circuitry (124), a RAS buffer (102), refresh counters (106), address buffers (104), row decoders (108), precharge circuitry (120) producing shorting clocks (128), and a refresh detector circuit coupled to the Latch P circuitry to provide a restore finished (RF) signal indicative that a refresh cycle is substantially completed. Burst refresh mode entry circuitry (140) detects proper conditions for entering burst refresh mode. An auto-refresh burst refresh mode circuit (136) causes the RAS buffer (102) to generate a new internal RAS signal. Burst refresh mode logic (134) has counters to count the number of rows that have been refreshed. The system self-times the refreshing by responding to the restore finished signal. A delay circuit (130) interposes a short delay for the precharge before another row is automatically refreshed in the burst refresh mode. Battery back-up mode circuitry (132) is partially disabled. <IMAGE> |
