| 摘要 |
PURPOSE:To house a large chip in a small package, to reduce thermal stress of a wire bonded section, to obtain a lead burying length and to decrease the influence of a mechanical stress at the time of forming leads by arraying a bonding pad substantially at the center of an LSI chip on a linear line in the longitudinal direction of a chip. CONSTITUTION:A plurality of bonding pads 1 are provided on a rectangular LSI chip 5, leads 7 are radially arranged on the peripheral edge of the chip 5, and the pads 1 are electrically connected by wire bonding to one ends of the leads 7. The pads 1 of a semiconductor device having a resin sealing package 9 of such a structure are arrayed substantially at the center of the chip 5 on a linear line in the longitudinal direction of the chip 5. For example, the surface of the chip 5 except the pads 1 is covered with a heat resistant electric insulating film 10, the covered surface and the rear face of a lead frame 6 are bonded fixedly in such a manner that the pads 1 oppose the ends of the leads 7, and the pads 1 are wire bonded to the end surfaces of the leads 7. |
