| 摘要 |
An iterative division technique which forms plural quotient bits per iteration. A data processing apparatus (1100) includes a first register (1101) storing the divisor, a second register initially storing the numerator (1103), a plurality of full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) and an equal number of negative detectors (1122, 1123, 1124, 1125, 1126, 1127, 1128), and a loop counter (1131). Initially the full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) compute each integral product of the divisor not a power of 2 between 1 and 2M-1 inclusive, where M is the number of quotient bits to be computed. These factors are stored in latches (1144, 1146, 1147, 1148). The full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) next subtract in parallel each integral product of the divisor between 1 and 2M-1 inclusive from the most significant bits of the numerator. Negative detectors (1122, 1123, 1124, 1125, 1126, 1127, 1128) connected to each full adder (1112, 1113, 1114, 1115, 1116, 1117, 1118) indicate the first non-negative difference, which determines plural bits of the quotient and a partial remainder. This process is repeated with partial remainder left shifted M places employed as the numerator a number of iterations based upon the size of the numbers employed and the number of bits per iteration. For signed division the sign of the quotient is set as the exclusive OR of the detected (1102, 1104) respective signs of the numerator and the divisor.
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