发明名称 |
CMOS logic gate clamping circuit |
摘要 |
A gate clamping circuit is disclosed that includes a logic gate and a bias circuit arrangement. Through this clamping circuit the speed of operation of the circuit during both low to high and high-to-low transitions of the output signal are optimized while power consumption is minimized.
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申请公布号 |
US5442304(A) |
申请公布日期 |
1995.08.15 |
申请号 |
US19930137437 |
申请日期 |
1993.10.15 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
WONG, JACK T.;FONTANA, FABIANO;CHAN, MARTHA |
分类号 |
H03K19/00;H03K19/017;(IPC1-7):H03K19/01 |
主分类号 |
H03K19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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