| 摘要 |
PURPOSE:To provide technique for easily generating the narrow pulse sequence of clocks. CONSTITUTION:A flip-flop EL is reset based on a logical change, which is caused by the logical change of an output terminal for a clock signal output, at the far end part of a clock transmission path 10, and a clock generating circuit 20 is formed so as to regulate the pulse duration of diagnostic clock signals phim and phi. Thus, the rear end of the clock signal is exactly decided, the configuration of the clock generating circuit 20 is simplified, and the area to be occupied is reduced. |
