Interface circuit for management of data transfer between processor

摘要

The interface circuit (30) has a storage and a controller. The storage can be switched between the bus (12) of a processor (10) requesting data and the bus (22) of a processor (20) which is to reply. The storage stores the access address for the responding processor and the transferred data. In case of a write request, this is data to be stored in the access address of the responding processor. For a read request, it is data obtained from the access address. The controller controls the storage and communicates with the requesting and responding processors. It performs the data transfer, leaving the requesting processor to continue its work. When data transfer is complete, the control device signals the requesting processor via an interrupt that it is ready to accept another request.