| 摘要 |
PURPOSE:To make it possible to process unificatively the rewrite of conversion information to the main memory of each processor by providing a bus for signals which controls plural processors. CONSTITUTION:Each of processors 45, 55, 65 and 80 connected through processor bus 90 is constituted by central processing unit 555, memory protect circuit 556, main memory 557, processor bus connection circuit 554, etc., and memory 557 has a write-protected area at a normal operation time, and circuit 556 has a function to prevent unit 555 from operating the write to the write-protected area. Then, when one of these processors is assigned by busses 93 and 97 for signals, the memory protect function is released in 555 to operate the release function in a prescribed time, and further, the selection of permission or inpermission for operating busses 93 and 97 can be controlled by a switch of system monitor unit 71. |
