| 摘要 |
An address generator capable of generating address data for sequentially accessing a memory from a selected memory location has a first dip switch for manually setting first reference address data and a second dip switch for manually setting second reference address data, a first counter for loading the first reference address data from the first dip switch, and in synchronization with a first clock pulse, producing lower M-bit address data, a second counter 20 for loading the second reference address data from the second dip switch, and in synchronization with a second clock pulse, producing higher M-bit address data, an AND gate for generating a second clock pulse, and a control unit for generating a first and a second control signals, wherein the first control signal is applied to the first and the second counters and the second control signal is applied to the AND gate. <IMAGE> |
