| 摘要 |
A delay chain having a known number of delay elements providing various delayed outputs of its input, a first and a second register set, and preferably, an array of multiplexors, are provided to measure the frequency of a digital signal, and the high and low time of its period. The digital signal to be measured is provided to the delay chain as input. A first and a second sample of the various delayed outputs are taken at the beginning and the end of a known time period, and stored in the first and second registers, one delayed output per register bit. The sample results stored in the register sets are read out through the multiplexors, and used to determine the frequency of the digital signal being measured, and the high and low time of its period.
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