| 摘要 |
PURPOSE:To improve the operation reliability of a switchboard, etc., by substantially removing causes of an error pulse and error-connection with the order-transmission inhibit interval shortened, by enabling a CPU to send out an order after detecting status information. CONSTITUTION:When output 00 of signal distributor SD becomes ''1'', FF F/F00 of switching status display register R1 is set, and its output Q00 is made ''1'' to operate switching relay T00. Next, after the transistion of the contact of T00 ends, contact (t ) of T00 also finishes its transition, and F/F00 is reset to turn Q00 into ''0''. Namely, F/F00 is set (Q00 is ''1'') from the switching start of T00 until its switching end, Q00 is detected by central controller CC, and this inhibits the transmission of all orders relating to T00 during the period of ''1''. This order inhibit period, which is the time for the actual switching of T00, is shortened to approximate 100mus to lms. Therefore, the absence of a dial pulse of 15ms to 35ms in pulse width can be eliminated. |
