SEMICONDUCTOR MEMORY DEVICE WITH MULTI-ECC

摘要

The device comprises ;a memory cell array which is partitioned into a number of sub-cell arrays containing both normal memory cells and parity cells; a number of sense amplifier groups of which each sense amplifier group is connected to one of the sub-cell arrays for performing sensing operation of cell data from the sub-cell arrays; a number of error checking and correcting circuits which are connected to one of the sense amplifier groups for repairing syndrome bits within the cell data; and output decoders which are connected to an output of one of the error checking and correcting circuits. When the device is operated in a normal mode, one of the sub-cell arrays is selected. However, when the device is operated in a page mode, all sub-cell arrays are selected.