| 摘要 |
PURPOSE:To realize a PLL circuit where a lock-up characteristic is higher speed by supplying the reference voltage from a reference voltage generation means to the reference voltage side of a filtering means. CONSTITUTION:When the setting of a frequency division ratio is switched, the switch is adjusted by a gain setting variable resistance 9 so that the gain of a D/A converter 4 may be equal to the gain of a voltage controlled oscillator (VCO) 5. Every time the setting of the frequency division ratio is switched, a capacitor C4 is charged up by the output voltage of a converter 4. As a result, the change of the voltage of the input terminal of the VCO 5 becomes equal to the change of the output voltage of the converter 4. Therefore, because the time to be required for the change of the voltage of the input terminal of the VCO 5 depends on the only time constant determined by the output resistance of the converter 4 and the capacitor C4, the speeding-up of lock-up time can be performed without changing the characteristic of a PLL circuit by reducing the values of the output resistance of the converter 4 and the capacitor C4. |
