| 摘要 |
<p>PURPOSE: To provide the power managing device of a computer system in which the supply of a power to a system oscillator can be controlled, and power consumption can be reduced. CONSTITUTION: An output signal from a power managing device 110 is applied, and when a computer system 100 is in a power saved and stopped state, an outside system oscillator which generates a system clock signal is turned off, and when this computer system is resumed, and it is in a ready state, this outside system oscillator is turned on. A counter is provided, and the latency of the output signal is controlled when the power managing device inputs and outputs the stopped state. This latency generates a time when a microprocessor clock and/or the other clock signals related with the system oscillator are turned into an operation stopped state before the oscillator is turned into the operation stopped state, and a time when the oscillator is stabilized before the clock signals are resumed. As a result, the power consumption of the computer system can be reduced, and the proper clock generation for this computer system can be maintained.</p> |
