| 摘要 |
PURPOSE:To realize the clock recovery circuit operated stably with high frequency accuracy even against a reception signal whose transmission speed is high with a complete digital circuit. CONSTITUTION:After a reception signal is converted into a digital signal by an A/D converter 1, a clock phase error detector 2 obtains a clock phase error. An output from a loop filter 3 is divided into high-order bits and low-order bits and the low-order bits not loaded to a down-counter 4 are integrated by an integration device 6. Only when the integration device 6 overflows, an adder 7 adds '1' to the high-order bits being an output of the loop filter and provides an output of a load value to the down-counter 4. The down-counter 4 counts high speed clocks outputted from an oscillator 5 and provides an output of a zero detection signal every time the loaded value reaches zero to set the zero detection signal to be a new load value signal and as a sampling clock for the A/D converter 1. |
