发明名称 CLOCK PATH CONTROL SYSTEM
摘要 PURPOSE:To prevent an in-equipment clock from being stopped and all signals from being interrupted by selecting an internal oscillator capable of absorbing destination difference through the stuff operation by an opposite equipment when an in-station clock of both systems is interrupted from a clock supply device in a synchronous digital hierarchy(SDH) communication equipment. CONSTITUTION:Clock interrupt detection circuits 11a, 11b of systems 0, 1 in reception sections monitor an in-station clock having a redundancy from a clock supply device. When both the systems detect interrupt of clock input, a selector 14 is used to select an internal oscillator 15 having a frequency accuracy capable of absorbing difference from the frequency of the in-station clock by using the interrupt signal as a trigger through stuff operation of an opposite equipment. Thus, even when both systems of clocks having a redundancy from the clock supply device are interrupted, an in-equipment clock is supplied to an OH processing section 23 to send normal main signal data to the opposite equipment.
申请公布号 JPH07202866(A) 申请公布日期 1995.08.04
申请号 JP19930334279 申请日期 1993.12.28
申请人 NEC CORP 发明人 ASAKURA NORIYUKI
分类号 H03L7/00;H04J3/00;H04J3/06;H04L7/00 主分类号 H03L7/00
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