| 摘要 |
PURPOSE: To improve the performance of a set associative cache at a 1st level. CONSTITUTION: A microprocessor 10 includes a microprocessor core 15 placed on a semiconductor die and a set associative 1st level cache 30. A substitute cache 60 is placed on the same die and connected to the cache 30. In a 1st level cache miss mode, the 1st level entry is disused and stored in the cache 60. When the 1st level cache miss occurs, the cache 60 is checked. If the cache 60 has a hit, the hit entry is sent to the cache 30 and stored there. If the cache misses occur at both caches 30 and 60, a main memory access is started to fetch the desired entry. Then the fetched desired entry is sent to the cache 30 and stored there. |
