A DEMODULATOR FOR FREQUENCY SHIFT KEYED SIGNALS

摘要

A demodulator (414) for improving bit error rate performance consists of a zero threshold comparator circuit (502), a first threshold detector circuit (508), and a second threshold detector circuit (504). The first threshold detector circuit (508) compares the frequency information signal to a predetermined threshold, which is selected to optimize bit error rate performance. The second detector threshold circuit (504) is used to ensure that an alternating bit pattern has occurred. The demodulator (414) also includes a control device circuit (516) for coupling a plurality of bits (522) from a zero threshold comparator (502) to the output of the control device as a decision output signal (416) when the frequency information signal falls outside of either the first or second detector thresholds (508, 504). If the frequency information signal falls within both thresholds of the detector devices, then the decision output signal (416) for the control device (516) is formed by inverting the bit decision from the previous bit interval.