Phased locked loop synthesizer using a digital rate multiplier reference circuit.

摘要

A phase locked loop synthesizer (20) for generating a digitally programmable, continuous wave signal comprises a rate multiplier (26) and divider (28) connected in a reference signal path to a phase detector ( 42). The rate multiplier and divider generate a reference signal which is programmable to any of a set of regularly spaced frequencies having exact decimal representations. The divider limits the peak-to-peak phase deviation of the rate multiplier. The phase detector locks a synthesized signal generated by a variable frequency oscillator (44) to the phase of the programmed reference signal. A spur filter (60) connected to the phase detector output (46) reduces spurious frequencies in the phase detector output. <IMAGE>