| 摘要 |
The testing of an n-bit encoder (14) and an n-bit decoder that collectively comprise a CODEC is performed by an apparatus including an n+1 bit counter (18) for generating a count, for generating an overflow signal once the counter has counted one beyond 2<n>-1. A digital comparator (26) is provided for comparing the count of the counter to a code generated by the encoder when the same is supplied with an input voltage. A logic circuit (24,25) is provided for sampling the counter to run freely for the purposes of testing the decoder and for enabling the counter to count each time the counter count equals the encoder code for purposes of testing the encoder. <IMAGE> |
