| 摘要 |
In a radio receiver for electronically selecting channels by way of the frequency synthesizer system, a highspeed channel scanning operation is realized. A CPU (central processing unit) detects both an SC (squelch control) signal derived from a squelch circuit and an output voltage from a frequency discriminator. The CPU controls data to be supplied to a PLL (phase-locked loop) circuit employed in a frequency synthesizer so as to perform a channel scanning operation scanning three channels concurrently. When the CPU judges that a desirable reception signal is detected based on a change in the SC signals during the concurrent scan operation. This CPU determines at which channel, the scanning operation is stopped among three channels: the central channel of the three channels searched during the concurrent scan operation, a channel higher in frequency than this searched channel by 1 step, and a channel lower in frequency than this searched channel by 1 step. Then, the CPU supplies PLL data corresponding to the channel at which the scanning operation is stopped into the PLL circuit employed in the frequency synthesizer.
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