| 摘要 |
A semiconductor SRAM device is provided wherein the electrical characteristics of the memory cell of the SRAM device is enhanced by decreasing the OFF-current and by increasing ON-current of PMOS thin film transistor (TFT) load elements. An offset region is formed between the drain and channel regions of the PMOS TFT. The gate is formed below (or above) the channel region of the PMOS TFT, and an insulating layer is formed below the gate. A ground potential Vss conductive layer is formed below the insulating layer, facing the offset region, to thereby operate as a gate for the offset region. The ground potential of the conductive layer facing the offset region of the PMOS TFT is constantly ON because of the gate operation of the ground potential conductive layer. A higher ON/OFF current ratio results, and the electric characteristics of the PMOS TFT load elements and therefore the SRAM device are thereby enhanced.
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