| 发明名称 |
Method of fabricating gate stack having a reduced height |
| 摘要 |
An integrated circuit device having reduced-height gate stack is fabricated by using a patterned oxide hard mask to pattern the underlying metal layer. The oxide mask is removed and the patterned metal is subsequently used as a mask to etch the polysilicon layer.
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| 申请公布号 |
US5438006(A) |
申请公布日期 |
1995.08.01 |
| 申请号 |
US19940176600 |
申请日期 |
1994.01.03 |
| 申请人 |
AT&T CORP. |
发明人 |
CHANG, CHORNG-PING;LEE, KUO-HUA;LIU, CHUN-TING;LIU, RUICHEN |
| 分类号 |
H01L21/8234;H01L21/28;H01L27/088;(IPC1-7):H01L21/823 |
主分类号 |
H01L21/8234 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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