Direct memory access controller for handling cyclic execution of data transfer in accordance with stored transfer control information

摘要

A direct memory access controller coupled to a system bus of a system for controlling data transfers through a channel includes the following. A request handler receives a transfer request generated by a device connected to the system bus. A transfer control information register stores transfer control information used for obtaining transfer control information necessary for executing the data transfer by a next transfer request supplied from the request handler. A temporary register stores the transfer control information necessary for processing the next transfer request. A transfer control information setting circuit generates the transfer control information necessary for processing the next transfer request on the basis of the transfer control information registered in the transfer control information register during the data transfer by the present transfer request and then renewing the transfer control information and-temporary registers with the generated transfer control information. A transfer execution circuit executes the actual data transfer through the system bus in accordance with the transfer control information registered in the temporary register, which is output to the system bus therefrom.