| 摘要 |
PURPOSE:To provide the arithmetic unit which can shorten zero detecting time by performing zero detection parallelly with arithmetic processing. CONSTITUTION:The arithmetic unit is provided with a computing element and a zero detector. EOR circuits 11a1-11a8 perform logical arithmetic by inputting the bits of binary numerals A and B at the same digit. NOT circuits 13a2-13a8 respectively input the outputs of the EOR circuits 11a2-11a8 and output inverted signals. NOR circuits 12a1-12a7 perform logical arithmetic by inputting the bits of the binary numerals A and B at the same digit. When the outputs of the NOR circuits 12a1-12a7 show logic '1', selectors 14a2-14a8 select the outputs of the NOT circuits 13a2-13a8 but when they show logic '0', the outputs of the EOR circuits 11a2-11a8 are selected. An all-zero detection circuit 16 detects that the arithmetic result of the computing element is zero by deciding whether the arithmetic result S1 and the outputs of NOT circuits 15a2-15a8 show logic '0' or not. |
