发明名称 INTER-CARRIER DELAY ADJUSTMENT CIRCUIT
摘要 PURPOSE:To obtain the delay time adjustment circuit transmitting correctly a data signal string of other carrier even when an error takes place in any carrier when the data signal string of STM-N frame configuration on which plural pointers and plural sets of real information are multiplied by using the multi-carrier digital radio transmission system. CONSTITUTION:A fixed delay circuit 14 corresponding to a specific Carrier 1, selection circuits 15, 16 corresponding respectively to other carriers 2, 3 and fixed delay circuits 17, 18 are used to generate reference clocks 221, 222, 223 and reference frame pulses 321, 322, 323. The selection circuit is controlled by a pointer discrimination section 13 based on a pointer detected by a pointer detection circuit 12 and selectively provides any of a reception clock 201 obtained from the specific carrier, an output frame pulse 301, reception clocks 202, 203 obtained from each carrier and output frame pulses 302, 303.
申请公布号 JPH07193611(A) 申请公布日期 1995.07.28
申请号 JP19930330386 申请日期 1993.12.27
申请人 NEC CORP 发明人 MUTO HIDEYUKI
分类号 H04L27/38;H04J3/00;H04J4/00;H04L7/00 主分类号 H04L27/38
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