ARBEITER DELAY CIRCUIT FOR MULTIPROCESSOR SYSTEM

摘要

The circuit provides accurate and fast data processing among the system processors by preventing the data collision, which is usually generated in the shared memory, of the multi-processor system. The circuit includes: (a) an address decoder(20) which designates the memory location in the system processor(10); (b) a status register(30) which generates level signal according to the selected data through the data line; (c) a bus arbiter(40) which generates bus control signals by using the address decoder output; (d) a master set module(50) which combines the level signal of the status register(30) and the bus request signal to generate output signal.