Circuit for redn. of power dissipation in e.g. VLSI memory chip

摘要

The chip incorporates a number of identical current evaluation circuits (SB1-SBm) and a common bus line system (B1-Bm) for internal latch cells (Ln, Ln+1 etc.) each having a switching transistor (T1) and a line from control logic (STL). Each evaluation circuit converts a current signal into a voltage signal for another latch cell (LO) in which the information (BO1) is stored. Another bus line (Bm+1) conveys control signals from a shift register (DR) to another evaluation circuit (SBm+1) to interrupt the current signals immediately after their conversion into voltages.