Verfahren zum Test von digitalen Speichereinrichtungen

摘要

The invention relates to a store test especially suitable for stores in which the number of address bits is greater than that ofthe data bits. Addressing errors affecting the higher-order address bits in such stores cannot be detected by prior art store tests. According to the invention, the value ADR(0...DN-1)XOR ADR(D...N) is entered in each storage cell, i.e. the sequence of the numerical values entered depends on the address field (Address bits D...N) and addressing errors in the higher-order address lines are detected.