Anordnung zur Synchronisierung der Ausgangspulse einer Schaltung mit einem Eingangstakt.

摘要

A device for synchronizing the output test pattern signals (14) of a test circuit with the clock signal (14) of a device under test (DUT). The invention uses a programmable delay (56) in the feedback loop of a phase locked loop system (20) to adjust the phase of the test pattern signals (14) to be synchronized with the clock (12) of the device under test (DUT).