High-speed test pattern generator for semiconductor test system

摘要

The test pattern generator has a series to parallel circuit configuration in order to convert an instruction signal (ix) of serial form in the programme memory (71) into a number of signals (n) of parallel form e.g. the signals (i0,i1,i2,i3). A signal processing module (100) containing the instruction signal processors (101,102,103) and registers (111 to 122) are subject to a control cycle determined by the clock (72). An arithmetic module (200) comprises the arithmetic units (201 to 204) and register (205) allocated to the separate signal paths (X0 to X3) terminating in inputs to a multiplex converter which re-aligns the output signals (X) to serial form at increased transmission rate.