发明名称 |
Verfahren und System zur Bestimmung der Zusammensetzung einer integrierten Schaltung. |
摘要 |
To assist the design of ASIC-type integrated circuits, their functions are simulated in a parallel-architecture machine (10) which includes, in particular, transputers. The allocation of the resources of this parallel-architecture machine are monitored (21-23) in order to evaluate the performance of the ASIC circuit to be produced. <IMAGE> |
申请公布号 |
DE69400008(D1) |
申请公布日期 |
1995.07.27 |
申请号 |
DE1994600008 |
申请日期 |
1994.03.18 |
申请人 |
SGS-THOMSON MICROELECTRONICS S.A., GENTILLY, FR |
发明人 |
LE VAN SUU, MAURICE, F-75116 PARIS, FR |
分类号 |
G06F11/34;G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F11/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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