STORAGE NODE OF VLSI CIRCUIT MANUFACTURING PROCESS

摘要

This method reduces the area of cell and maximizes the capability of the capacitor of semiconductor device. The method comprises the steps of: forming the first charge storage electrode conducting material (7) on the inter-layer insulating layer (6) and forming a charge storage electrode mask (9) sequentially; forming a charge storage electrode contact mask (10) and etching the first charge storage electrode conducting material sequentially; forming the second charge storage electrode conducting material (11); forming a charge storage electrode contact hole by etching and forming the third charge storage electrode conducting material (12) which is connected with a source electrode (5) through the contact hole; and etching back the third charge storage electrode conducting material and forming the third charge storage electrode conducting material spacer (12') in the side wall of the second charge storage electrode conducting material spacer sequentially.