发明名称 |
Data processor with an efficient bit move capability and method therefor. |
摘要 |
<p>A data processor (40) includes source (60) and destination (61) address generation units (AGUs) to update source and destination addresses for efficient digital signal processing (DSP) functions. The data processor (40) includes an instruction decoder (41) which recognizes a bit movement instruction, which is frequently encountered in data interleaving operations. In response to the bit movement instruction, the instruction decoder (41) causes the source (60) and destination (61) AGUs to update their present addresses using variable offset values. The instruction decoder (41) further causes a bus controller (44) to convert these bit addresses to corresponding operand addresses and bit fields. The bus controller (44) accesses source and destination operands using the operand addresses. The instruction decoder (41) then causes an execution unit (45) to transfer a bit from the source operand indicated by the source bit field to a bit position of the destination operand indicated by the destination bit field. <IMAGE></p> |
申请公布号 |
EP0664508(A2) |
申请公布日期 |
1995.07.26 |
申请号 |
EP19950100682 |
申请日期 |
1995.01.19 |
申请人 |
MOTOROLA, INC. |
发明人 |
WENG, CHIA-SHIANN;ANDERSON, DONALD C.;ASTRACHAN, PAUL M.;KUENAST, WALTER U.;CURTIS, PETER C.;WENG, KENNETH C. |
分类号 |
G06F9/30;G06F9/308;G06F9/315;G06F15/78;(IPC1-7):G06F9/315 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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