| 摘要 |
forming n--type epitaxial layer (3), buffer oxide layer (4), and nitride layer (5) on the n+-type well (2); forming an activation region (3a), forming device isolating oxide layer (6) which is located between activation regions, and forming an emitter electrode (10a) on the n--type epitaxial layer sequentially; etching selectively the n--type epitaxial layer which has an exposed surface and etching the n+-type well with some depth sequentially; forming sidewall oxide layer (15) on the side wall of the device isolating oxide layer, sidewall nitride layer (14), and the n--type epitaxial layer; spreading n+-type polycrystal silicon layer to contact a collector electrode (19); forming thermal oxide layer (20) on the surface of the collector electrode to isolate the collector electrode from a base electrode (23); and spreading a low temperature deposited oxide layer (24) and forming an opening to contact metal sequentially.
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