Input transition detection circuit for zero-power part

摘要

An input transition detection circuit for detecting when an input signal switches states, the input transition detection circuit then providing a time delay signal at a time delay signal node to enable a zero-power part to wake up from a low power mode. The input transition detection circuit includes two inverters and four transistors compared to the two inverters and nine transistors utilized in previous circuits. The two inverters are coupled in series for receiving and delaying the input signal. A first p-channel transistor has its source coupled to receive the input signal and gate coupled to the output of the two inverters. A second p-channel transistor has its source coupled to the output of the two inverters and gate coupled to receive the input signal. A first n-channel transistor is coupled to the drain of the first and second p-channel transistors and provides a current sink which draws less current than either the first or second p-channel transistors providing a voltage to control the gate of a second n-channel transistor. The second n-channel transistor connects the time delay signal node to ground. The second n-channel transistor enables the input transition detection circuit to be faster than previous circuits since only one transistor connects the time delay signal node to ground.