发明名称 Manufacturing method or an exposing method for a semiconductor device for a semiconductor integrated circuit device and a mask used therefor
摘要 One object of the present invention is to provide the reduced projection exposure method which enables the exposure of various and fine patterns in manufacturing process of semiconductor devices or semiconductor integrated circuit devices. Structure of the present invention to attain the above object is to carry out the reduced projection exposure using a phase shift mask provided with a prescribed correction pattern on the end of the mask pattern domain of a constant mode or the boundary of the mask pattern domain of plural modes. According to this structure, as the end effects etc. are canceled by the correction pattern, the various and fine patterns can be exposed.
申请公布号 US5436095(A) 申请公布日期 1995.07.25
申请号 US19920912511 申请日期 1992.07.13
申请人 HITACHI, LTD.;HITACHI VLSI ENGINEERING CORP. 发明人 MIZUNO, FUMIO;MORIUCHI, NOBORU;SHIRAI, SEIICHIRO;MORITA, MASAYUKI
分类号 G03F1/08;G03F1/00;G03F1/14;G03F1/30;G03F1/68;G03F7/20;H01L21/027;H01L21/30;(IPC1-7):G03F9/00;G03F9/02 主分类号 G03F1/08
代理机构 代理人
主权项
地址