发明名称 Semiconductor integrated circuuit device of dual configuration having enhanced soft error withstanding capacity
摘要 A semiconductor integrated circuit device has a dual configuration involving a first latch circuit and a second latch circuit that are connected in parallel with each other. The first latch circuit is provided with an input terminal to operate the first latch circuit independently of the second latch circuit. This semiconductor integrated circuit device is capable of individually testing the latch circuits of the dual configuration, to ensure the merit of the dual configuration.
申请公布号 US5436572(A) 申请公布日期 1995.07.25
申请号 US19930109518 申请日期 1993.08.20
申请人 FUJITSU LIMITED 发明人 SUGIYAMA, EIJI
分类号 H01L21/8249;H01L27/06;H03K3/037;H03K19/003;H03K19/173;(IPC1-7):H03K19/003 主分类号 H01L21/8249
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