| 摘要 |
PURPOSE:To surely perform a data transfer by eliminating the omission of data due to the generation of the phase difference of a clock by having a clock phase difference detection circuit in a data transfer device where data is inputted/outputted synchronizing the data with the same frequency or demultiplied frequencies. CONSTITUTION:A reception side performs a sampling for the clock 1 on a transmission side by a clock 7 in a sampling circuit B. The sampling is performed by the rise and fall of the clock 7. In a phase difference detection circuit C, the phase difference is detected by a sampling result 3 and the result 4 of the phase difference is outputted to a data latch control circuit D. The data latch control circuit D generates the proper latch timing of received data by the result 4 of the phase difference detection and outputs the timing to a data latch circuit. |
