FIFO CIRCUIT INTERFACING WITH CPU

摘要

The device provides an efficient FIFO circuit which performs input/output function using a common pointer. The device includes: (a) a latch which stores data by the CPU write signal and maintains data until the next write signal generation; (b) a FIFO controller which is activated and synchronized by the write cycle falling edge and the clock signal respectively; (c) an up/down controller and a decoder which generate the FIFO address signal and full/flag signal respectively; (d) a FIFO register which generates data signal and address signal by the external control signal.