| 摘要 |
PURPOSE:To provide a basic cell wherein more cells than required are not used and a chip area is not occupied when an SRAM is constituted in a gate array type semiconductor integrated circuit device. CONSTITUTION:The title device includes a P-channel MOS transistor region 1 for realizing a basic logic function, an N-channel MOS transistor region 2, a gate electrode 3 for each MOS transistor and a first layer power supply wiring 4 for supplying source electric potential of a P-channel MOS transistor, a first layer ground wiring 5 for supplying source electric potential of an N- channel MOS transistor and a second layer power supply wiring 6 or a second layer ground wiring 7 extending in a vertical direction to a 1ALVDD/GND transverse bus wiring thereof. An N-channel transistor 8 which is used as a transfer gate when one bit cell of an SRAM is constituted is arranged immediately below the second layer power supply/ground wiring. |
