发明名称 |
LOADING/STORING FUNCTION UNIT OF MICROPROCESSOR AND APPARATUS FOR INFORMATION PROCESSING |
摘要 |
PURPOSE: To perform plural load operations in parallel and to perform the store transfer operation by a super-scalar microprocessor provided with a load/ store function unit and a corresponding data cache. CONSTITUTION: A load/store function unit 134 includes plural entries RS0 to RS3 of a holding station 124, which are accessed in parallel and are coupled to a data cache 150 in parallel, and a store buffer circuit 180 having plural buffer entries SB0 to SB3. Store buffer entries are constituted so as to provide such first-in first-out buffer that the output from a lower-order entry of the buffer is given as the input to a higher-order entry. |
申请公布号 |
JPH07182167(A) |
申请公布日期 |
1995.07.21 |
申请号 |
JP19940260699 |
申请日期 |
1994.10.25 |
申请人 |
ADVANCED MICRO DEVICDS INC |
发明人 |
UIRIAMU EMU JIYONSON;DEIBITSUDO BII UITSUTO;MIYURARI CHINAKONDA |
分类号 |
G06F12/08;G06F9/312;G06F9/38;(IPC1-7):G06F9/38 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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