| 摘要 |
<p>The communication system links together n slave processors (P1, P2, ... Pn) and a master processor (Pm+1). It has a first bus for data transmission (1) and a second serial signalling bus (2). This is the seat of a synchronous signalling frame consisting of time intervals (IT) allowed to the processors, and devices for synchronising the time intervals in the processors. Comparison circuits are provided for marking in each processor the cyclical appearance of the IT which is allowed to that processor. A second comparison circuit is provided for marking each IT within the master processor.</p> |
