Interdependency control of pipelined instruction processor using comparing result of two index registers of skip instruction and next sequential instruction

摘要

An apparatus for and method of controlling branching conditions within a pipelined instruction processor. For jump instructions, a memory is used to store the target address of branches actually taken as a function of the absolute address of the jump instruction. The next time the same jump instruction is executed, the branch is assumed and the target address is supplied to the instruction pipeline for prefetching of the target instruction. If the conditional branch instruction is a skip instruction, interdependency of the Nth and N+1st instructions are determined by comparison of the index register fields. If no dependency is found, fully pipelined operation is continued. If a dependency is found, the system is depiped for one clock cycle to prevent the N+1st instruction from using an index register which has not been updated as anticipated by the software developer.