发明名称 Circuit for confirming a connection route of address control memory
摘要 A circuit for confirming a connection route of an address control memory includes a data memory, an address counter and the address control memory. The address control memory includes a reading memory for storing data to an address which is a respective position of the time-division multiplexed data in time slots given when the time-division multiplexed data is read from the data memory as an output data and the data is a respective position of the time-division data in the time slots given when the time-division multiplexed data is written into the data memory as input data. A writing memory is provided for storing data to an address which is a respective position of the time-division multiplexed data in time slots given when the time-division multiplexed data is written to the data memory as input data, and the data is a respective position of the time-division multiplexed data in time slots given when the time-division multiplexed data is read from the data memory, thereby specifying from the time slot position of data at the time of reading, the time slot position of data at the time of writing, and specifying from the time slot position of data at the time of writing, the time slot position of data at the time of reading.
申请公布号 US5434857(A) 申请公布日期 1995.07.18
申请号 US19940205329 申请日期 1994.03.03
申请人 FUJITSU LIMITED 发明人 MORI, HIROAKI
分类号 H04J3/06;H04Q3/52;H04Q11/04;H04Q11/08;(IPC1-7):H04Q11/04 主分类号 H04J3/06
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