| 摘要 |
PURPOSE:To generate data train with optional length at high speed by device with a simple structure. CONSTITUTION:Data of 16 bits in parallel is stored in a first memory 12. A first shift/register 14 loads the data in parallel and converts it into data in series. A load controlling memory (a second memory) 22 save load controlling data of 16 bits of which optionally prescribed bit orders the loading. A second shift/register 24 loads the load controlling data and converts it into a load signal. An address producing device 10 supplies the address to the first and the second memories 12, 22. The first and the second shift/registers 14, 24 load the data based on the load signal. That is, the first and the second shift/registers 14, 24 load the data in parallel and the data in series simultaneously. |
